A digital value or bit has one of two states--zero or one. A digital word is a sequence of digital values or bits. By way of example, a sixteen bit digital word may look as follows: 0100111001010110. Computers operate by processing digital words. It is frequently necessary for a computer to compare two digital words to determine whether they are identical. For example, the comparison operation is necessary when processing addresses of a computer program. A digital word comparator is used in this situation to determine whether a specified address in a computer program matches an address at a cache memory location.
The comparison of two digital words must identify whether each bit in a first digital word is identical to a corresponding bit in a second digital word. Thus, if the two bits have identical values (they are both zero or they are both one) then a match exists. If a match does not exist (one bit is zero and the other bit is one, or one bit is one and the other bit is zero), then the comparison operation fails. The foregoing logical processing can be characterized as an exclusive-or operation. This processing can be summarized as follows:
______________________________________ "EXCLUSIVE-OR" TRUTH TABLE FOR A COMPARISON OPERATION BIT 1 BIT 2 OUTPUT ______________________________________ 0 0 0 0 1 1 1 1 0 ______________________________________
In the exclusive-or operation, the output is a zero when bit one and bit two match. Using an exclusive-or operation, for a match to exist between two digital words, all comparison operations must be satisfied. In other words, a logical zero value must be produced by all of the comparison operations. If this occurs, then a match hit signal is generated, otherwise a match miss signal is generated.
Typical processing variations result in different timing and delay characteristics for comparators. This is a problem because the output for each comparison operation is required at the same time. Thus, design complexity increases as efforts are made to produce uniform timing and delay characteristics among distinct logical circuits. This design complexity is typically accompanied by circuit fabrication complexity.
One prior art comparator performs the compare operation in response to an externally generated enable signal. In this prior art comparator, the input data signals meet predetermined setup and hold time requirements with respect to a clock edge. After the enable signal is generated, a mass compare operation simultaneously performs an exclusive-or operation between corresponding bits in the two digital words. To meet the predetermined setup and hold time requirements, additional complex circuitry is required to generate the enable signal. Moreover, having to meet predetermined setup and hold time requirements may cause the comparator to generate false match hit signals or false match miss signals in extreme cases.
Since the operation of comparing digital words is so prevalent in a computer, it is important to perform it efficiently. Efficiency continues to grow in importance as processors and memories operate at ever-increasing speeds.
In view of the foregoing, it would be highly desirable to provide a method and apparatus for performing a compare operation that operates at a faster speed and that accommodates variations in extreme cases. Such a circuit would reduce timing and delay problems. In addition, such a circuit would reduce design complexity and be easier to fabricate. Preferably, the circuit would operate at a high speed and would reduce the number of transistors needed for implementation.